Transforming the OpenHW High Performance Data Cache into a High Performance Instruction Cache
Akiho Kawada
Since CVA6/Ariane is highly modular by design, it is relatively easy to develop and integrate multiple L1 caches. Additionally, because CVA6/Ariane...
TinyParrot: A minimal BlackParrot RISC-V Multicore variant
Colin Knizek
TinyParrot is a BlackParrot RISC-V multi-core variant that aims to be small enough to fit onto educational FPGA development boards like the Pynq Z2....
OpenRISC Benchmarking and Performance improvements
lg314
This project concerns the benchmarking of the OpenRISC project's mor1kx and marocchino cores, and improving the latter by attempting to resolve a...
Arcilator Vectorization
Mohamed Atef
Add a vectorization support to Arcilator. An efficient vectorization pass will make Arcilator faster, as hardware designs often contain highly...
Integration of Silicon Compiler Microservices into the TL-Verilog Mode in VS-Code
Raj Aryan Singh
This project aims to enable the seamless integration of the Silicon Compiler's hardware design tools and flows within popular development...
Implementing RISC-V Cache Management Operation Extensions in OpenPiton
Suraj Shirvankar
The project aims to integrate RISC-V Cache Management Operation (CMO) extensions into the OpenPiton processor framework. This integration will...
Improving ATPG Fault Coverage in Fault
Youssef Kandil
The semiconductor industry, driven by Moore's Law, continuously pushes the boundaries of integrated circuit (IC) technology, leading to...
